Title :
A 1.0 Gbps clock and data recovery circuit with two-XOR phase-frequency detector
Author :
Kim, Dong-Hee ; Kang, Jin-Ku
Author_Institution :
Dept. of Electr. & Comput. Eng., Inha Univ., Inchon, South Korea
Abstract :
This paper describes a 1.0 Gbps clock and data recovery circuit with a simple PFD structure. The proposed circuit is based on a single loop controlled by a Phase Frequency Detector (PFD) which has two-XOR gates. The VCO composed of four differential buffer stages generates eight differential clocks each spaced by 45°. The PFD generates the VCO control signal by comparing two different phase clocks and input data. The phase frequency capture range of PFD is decided by VCO operating range which is 380-720 MHz. The circuit operates on 800 Mbps to 1.2 Gbps data rate under 2.5 V supply using 0.25 μm CMOS HSPICE simulation
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; data communication equipment; detector circuits; digital communication; high-speed integrated circuits; synchronisation; timing; 0.25 micron; 1 Gbit/s; 2.5 V; 380 to 720 MHz; 800 Mbit/s to 1.2 Gbit/s; CMOS ASIC; PFD structure; VCO control signal; clock/data recovery circuit; differential buffer stages; differential clocks; two-XOR phase-frequency detector; Charge pumps; Circuits; Clocks; Delay; Filters; Logic gates; Phase detection; Phase frequency detector; Signal generators; Voltage-controlled oscillators;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896943
