Title :
Exploration of multiple ICEs for embedded microprocessor cores in an SoC chip
Author :
Huang, Ing-Jer ; Kao, Chung-Fu
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
This paper explores architectural alternatives in the integration of embedded in-circuit emulation into a SoC (System-on-Chip) chip with multiple microprocessor (microcontroller) cores. The alternatives include distributed, centralized and hierarchical styles. Advantages and disadvantages of these alternatives are analyzed
Keywords :
application specific integrated circuits; computer debugging; industrial property; integrated circuit testing; logic testing; microcontrollers; SoC chip; centralized style; distributed style; embedded microprocessor cores; hierarchical style; in-circuit emulation; multiple ICEs; multiple microcontroller cores; Circuit testing; Clocks; Debugging; Digital signal processing chips; Ice; Logic testing; Microcontrollers; Microprocessors; System testing; System-on-a-chip;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896970
