Title :
Design-for-testability of the FLOVA
Author :
Youn, Daehan ; Song, Ohyoung ; Chang, Hoon
Author_Institution :
Sch. of Electr. & Electron. Eng., Chungang Univ., Seoul, South Korea
Abstract :
This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively
Keywords :
boundary scan testing; built-in self test; design for testability; digital signal processing chips; floating point arithmetic; integrated circuit design; integrated circuit testing; pipeline processing; FLOVA; I/O cell; IEEE 1149.1 boundary-scan testing; VLIW architecture; built-in-self-test; design-for-testability; embedded memory unit; flip-flop; floating point digital signal processor; floating point processing unit; full-scan design; pipeline operation; Acceleration; CMOS technology; Clocks; Design for testability; Flip-flops; Packaging; Registers; Testing; VLIW; Very large scale integration;
Conference_Titel :
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location :
Cheju
Print_ISBN :
0-7803-6470-8
DOI :
10.1109/APASIC.2000.896972
