Memory access reduction method for efficient implementation of fast cosine transform Pruning on DSP

In this paper, we propose a novel memory access reduction method to minimize the memory accesses due to weighting factors (cosine coefficients in the computation diagram of fast DCT pruning) and input points for implementing fast DCT pruning on DSP processors. The proposed method reduces the number of memory accesses in two steps: 1) Reduce the number of weighting factors and 2) Combine butterflies at two stages in fast DCT pruning diagram to form an efficient butterfly structure in one stage and calculate them. The proposed method is applied to implement Pruning FCT on TI TMSC320C64x DSP. Experimental results show that the proposed method can achieve average of 40% memory access reduction, 48.6% clock cycle reduction and 32.6% memory space saving for weighting factors to compute Pruning FCT on DSP comparing with the conventional implementation.