An investigation into the effects of the gate drive resistance on the losses of the MOSFET-snubber-diode configuration

This paper presents an investigation into the effects of the gate drive resistance on the losses of the MOSFET-snubber-diode (MSD) configuration commonly found in a power converter. An analytical loss model that takes the circuit stray inductances, MOSFET parasitic capacitances, and reverse-recovery characteristic of the freewheeling diode into consideration is derived to describe the interaction among the MOSFET, snubber and freewheeling diode during switching transitions. It is then used to study the effects of the circuit stray inductances, gate drive resistance and snubber on affecting the switching behavior, power loss distribution in the entire MSD configuration and voltage stress on the MOSFET. A sequence of steps will be given to illustrate how an optimal value of the gate drive resistance is determined, in order to minimize the overall loss of the MSD configuration for a maximum permissible voltage stress on the MOSFET. The loss model and method of determining the gate drive resistance are evaluated by comparing the theoretical predictions with the experimental results of a 1 kW, 230 V, 50/60 Hz boost-type power factor corrector. The performances of the MSD configuration with different types and brands of MOSFETs and freewheeling diodes will be studied.