DocumentCode
2797953
Title
Long retention time of embedded DRAM macro with thin gate oxide film transistors
Author
Fukuda, R. ; Miyano, S. ; Namekawa, T. ; Haga, R. ; Wada, O. ; Takeda, S. ; Numata, K. ; Habu, M. ; Koike, H. ; Takato, H.
Author_Institution
Syst. LSI Res. & Dev. Center, Toshiba Corp., Kawasaki, Japan
fYear
2000
fDate
2000
Firstpage
351
Lastpage
354
Abstract
This paper describes the advantages of the thin gate oxide transistors with negative word-line (WL) architecture implemented in the embedded DRAM macro. The macros with the negative WL architecture are fabricated as well as the macros with the conventional WL architecture. We found the retention time of the negative WL architecture is longer by more than 5 times than that of the conventional WL architecture
Keywords
CMOS memory circuits; application specific integrated circuits; memory architecture; random-access storage; embedded DRAM macro; long retention time; negative word-line architecture; thin gate oxide film transistors; Application specific integrated circuits; CMOS technology; Decoding; Impurities; Large scale integration; Logic testing; Random access memory; Threshold voltage; Transistors; Variable structure systems;
fLanguage
English
Publisher
ieee
Conference_Titel
ASICs, 2000. AP-ASIC 2000. Proceedings of the Second IEEE Asia Pacific Conference on
Conference_Location
Cheju
Print_ISBN
0-7803-6470-8
Type
conf
DOI
10.1109/APASIC.2000.896981
Filename
896981
Link To Document