A regularly structured parallel multiplier with non-binary-logic counter circuits

This paper presents a low-power, high-performance and highly regular parallel multiplier architecture along with novel CMOS implementation circuits. The superiority is achieved through utilizing a unique scheme for recursive decomposition of partial product matrices and a recently proposed non-binary arithmetic logic, as well as the complementary shift switch parallel counters. The non-binary logic operates 4-bit state signals (representing integer ranging from 0 to 3), where no more than half of the signal bits are subject to value-change at any logic stage, thus reducing circuit power dissipation. The proposed 64×64-b parallel multiplier possesses the following distinct features: (1) generating 64 8×8-b partial product matrices, instead of a single large one as commonly adopted by the existing designs; (2) comprising only four stages of bit reductions: first, by 64 identical 8×8 small parallel multipliers; second, by 16 identical arrays of small (6,2) parallel counters; and for the remaining two stages, by 4 and 1 identical arrays of (6,2) parallel counters respectively. A family of shift switch parallel counters, including non-binary (5,3), (6,3) and complementary (3,2), (6,2) and (8,2), are proposed for the efficient bit reduction; (3) using a final adder significantly simpler than a traditional large final adder