High Level Modelling and Design For a Microthreaded Scheduler to Support Microgrids

Microgrid CMPs, that is based on microthreaded processors, use hardware scheduling and synchronisation and have structures to support this that are distributed, fully scalable and which can support hundreds of microthreads per processor and their associated microcontexts. The chip has locality in communication wherever possible, and supports a globally-asynchronous locally-synchronous (GALS) design approach, where all its global communications are asynchronous, creating independent clocking domains for each microthreaded processor. Each microthreaded processor has its own instruction window and local register file, both of which are fully scalable. Any remote access is fully decupled from the pipeline operations including memory. This paper introduces the microgrid CMP architecture model and discusses in general terms how our approach meets the challenges facing CMP architectures. It also summarizes microgrid CMP performance simulations published elsewhere and presents a local scheduler and the microthreaded in-order pipeline.