Passing gate stuck-open fault testing in MOS combinational circuits

Author

Belkadi, Mustapha ; Mouftah, H.T.

Author_Institution

Dept. of Electr. Eng., Queen´´s Univ., Kingston, Ont., Canada

fYear

1990

fDate

12-14 Aug 1990

Firstpage

335

Abstract

A testable design for a passing gate when it is not used in a multiplexer type structure and subject to a stuck-open fault condition is presented. It is shown that the new approach can be extended to passing gate-based multiplexers for which a better testing scheme is ensured. The authors also demonstrate that not all passing gates need to be augmented using an additional MOS transistor, so that the circuit under study can be kept combinational while in the test mode. Finally, the test generation for isolated passing gates in the context of the PODEM algorithm is discussed

Keywords

MOS integrated circuits; automatic testing; combinatorial circuits; integrated circuit testing; integrated logic circuits; logic testing; MOS combinational circuits; PODEM algorithm; logic circuits; multiplexer type structure; passing gate; passing gate-based multiplexers; stuck-open fault testing; testable design; Automatic testing; Circuit faults; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; MOSFETs; Multiplexing; Test pattern generators; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1990., Proceedings of the 33rd Midwest Symposium on

Conference_Location

Calgary, Alta.

Print_ISBN

0-7803-0081-5

Type

conf

DOI

10.1109/MWSCAS.1990.140721

Filename

140721