Cluster based architecture synthesis minimizing the resources under time constraint

High performance using minimal resources has become a serious problem for digital signal processing (DSP) applications. The number of addressable registers is a significant obstacle for centralized architecture achieving high performance of DSP applications. In this paper, we propose a novel cluster based architecture synthesis algorithm, using minimal resources with time and register constraints, which adds a new cluster rather than inserts memory operations when registers are inadequate. By counting the register, inter-cluster communications and function units requirements during scheduling, the cluster with optimal performance is selected to schedule every instruction of the application. The redundant resources of the initial configuration obtained by our algorithm are further optimized. The experiments demonstrate that, compared with the centralized architecture synthesis, our approach achieves up to 224% improvement in success rate for general cases and up to 369% improvement for cases with tight constraints, and effectively reduces the resources usage.