Switching losses analysis in MHz integrated synchronous Buck converter to support optimal power stage width segmentation in CMOS technology

Power stage width segmentation has been verified to be effective to improve the efficiency of MHz integrated synchronous Buck converters (ISBC). However, the theoretical analysis of the relationship between the load current and the power stage width or the number of active baby cells had not yet been established. This paper suggests a breakdown analysis of the transient currents in power FETs and recommends one kind of physical based separation between charging/discharging loss and overlap loss. Furthermore, criteria of the Miller plateau are presented to interpret the difference about overlap loss between the control PFET turning on and off. Moreover, five typical types of energy dissipations due to the charging/discharging process of the parasitic capacitors in power FETs are classified so that the charge/discharge losses in four different switching events can be separately evaluated. On the basis of the aforementioned concepts and analysis, the number of the active baby cells necessary for the optimal power stage segmentation in an example ISBS for portable application can be theoretically predicted. The derived values match well with the simulation results.