• DocumentCode
    2798884
  • Title

    Backward Reasoning with Formal Properties: A Methodology for Bug Isolation on Simulation Traces

  • Author

    Komuravelli, Anvesh ; Mitra, Srobona ; Banerjee, Ansuman ; Dasgupta, Pallab

  • Author_Institution
    Dept. of Comp. Sc. & Eng., IIT Kharagpur, Kharagpur, India
  • fYear
    2011
  • fDate
    20-23 Nov. 2011
  • Firstpage
    238
  • Lastpage
    243
  • Abstract
    Automated methods for bug localization for hardware designs typically work on the design implementation to root-cause a given bug. This paper presents a novel debugging approach where instead of using the design implementation in the debugging process, we use causal deduction using formal properties scattered across the design to locate the bug. This has two advantages, namely, (a) the reasoning takes place in the property space instead of the state space of the implementation, which enhances scalability, and (b) new properties can be added in hindsight to perform what-if analysis, which is less expensive than modifying the implementation for each alternative. Experimental results demonstrate the scalability of the approach in debugging designs with large property suites.
  • Keywords
    computer debugging; formal verification; inference mechanisms; backward reasoning; bug isolation; causal deduction; debugging approach; formal property; hardware design; simulation trace; Algorithm design and analysis; Cognition; Computer bugs; Cost accounting; Debugging; Protocols; Scalability; Assertions; Bug localization; Verification;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Test Symposium (ATS), 2011 20th Asian
  • Conference_Location
    New Delhi
  • ISSN
    1081-7735
  • Print_ISBN
    978-1-4577-1984-4
  • Type

    conf

  • DOI
    10.1109/ATS.2011.54
  • Filename
    6114496