Title :
ICCAD-2005 International Conference on Computer Aided Design (IEEE Cat. No. 05CH37700)
Abstract :
The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; network routing and application specific NoC architectures; memory driven codes; arithmetic constructs; buffers and voltage islands; sequential circuit optimization; nanoelectronics; dynamic voltage scaling; biochips and DNA-based nanofabrication; circuit simulation; analog circuit design; power aware system architecture; software optimization; cellular array architectures; variability aware clocking; oscillator analysis; power noise and thermal issues; nanocomputing; extraction and modeling for interconnect structures; system-level variability modeling; high-level synthesis; model order reduction; statistical timing analysis; formal verification; hardware and software design of sensors; formal equivalence checking and system on chip.
Keywords :
analogue circuits; cellular arrays; circuit CAD; circuit optimisation; design for manufacture; digital arithmetic; electric sensing devices; formal verification; hardware-software codesign; logic design; nanoelectronics; network routing; network-on-chip; oscillators; power grids; reduced order systems; system-on-chip; DNA-based nanofabrication; RF testing; analog circuit design; analog testing; application specific NoC architectures; arithmetic constructs; arithmetic optimization; biochips; buffers and voltage islands; cellular array architectures; circuit layout; circuit simulation; design for manufacturing; design manufacturing interaction; digital testing; double-gated devices; dynamic voltage scaling; formal equivalence checking; formal verification; high-level synthesis; interconnect structures; logic synthesis; memory driven codes; memory optimization; model order reduction; nanocomputing; nanoelectronics; network routing; oscillator analysis; power aware system architecture; sensor design; sequential circuit optimization; software optimization; statistical timing analysis; system on chip; system-level variability modeling; variability aware clocking; Analog circuits; Cellular logic arrays; Circuit optimization; Design automation; Design methodology; Detectors; Digital arithmetic; Logic design; Oscillators; Reduced order systems; Routing;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560027
