DocumentCode :
2799210
Title :
SPIDER: simultaneous post-layout IR-drop and metal density enhancement with redundant fill
Author :
Leung, Kwok-Shing
Author_Institution :
Magma Design Autom. Inc., Santa Clara, CA, USA
fYear :
2005
fDate :
6-10 Nov. 2005
Firstpage :
33
Lastpage :
38
Abstract :
This paper presents SPIDER, a novel methodology that advantageously utilizes metal fill to simultaneously fulfil metal density requirements and reduce IR-drop of the power distribution network. This is achieved through the addition of partially redundant connections between metal fills and power meshes. Our technique is especially significant for 90nm process technology or below because (1) metal fill must now be done as part of the IC implementation flow due to its increasing impact on timing, (2) the tolerance for IR drop is tightening due to voltage scaling, and the increasingly conservative power mesh design to address IR-drop is adding significant burden on the available routing resources, (3) IR-drop is getting worse due to increasing design sizes, and (4) the large degree of design uncertainty demands IRdrop repair capabilities that can be applied after routing is completed. SPIDER addresses all these issues practically with little or no cost. Experimental results further demonstrated the robustness and effectiveness of our approach: SPIDER achieves an average IR-drop reduction of 62.2% in 16 designs of various sizes.
Keywords :
circuit layout CAD; circuit optimisation; integrated circuit layout; integrated circuit metallisation; integrated circuit yield; 90 nm; IR-drop reduction; IR-drop tolerance; SPIDER methodology; conservative power mesh design; metal density enhancement; metal density requirement; metal fill; partial redundant connections; power distribution network; redundant fill; simultaneous post-layout IR-drop; voltage drop; yield optimization; Algorithm design and analysis; Computer aided manufacturing; Computer applications; Design automation; Design optimization; Integrated circuit yield; Routing; Switches; Timing; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
Type :
conf
DOI :
10.1109/ICCAD.2005.1560036
Filename :
1560036
Link To Document :
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