Virtual Circuit Model for Low Power Scan Testing in Linear Decompressor-Based Compression Environment

Large test data volume and high test power consumption are two major concerns for the industry when testing large integrated circuits. Linear decompress or-based compression (LDC) is efficient in reducing test data volume, while X-filling during ATPG can efficiently reduce test power with low overhead. However, traditional X-filling methods cannot be reused in the LDC environment. In this paper, we propose a virtual circuit model to make the linear de-compressor transparent to the external testing. As a result, existing X-filling methods can be reused to reduce test power. Experimental results on benchmark circuits demonstrate the efficiency of the proposed approach.