Title :
The circuit design of the synergistic processor element of a CELL processor
Author :
Takahashi, O. ; Cook, R. ; Cottier, S. ; Dhong, S.H. ; Flachs, B. ; Hirairi, K. ; Kawasumi, A. ; Murakami, H. ; Noro, H. ; Oh, H. ; Onish, S. ; Pille, J. ; Silberman, J.
Author_Institution :
IBM Syst. & Technol. Group, Austin, TX, USA
Abstract :
A 32b 4-way SIMD dual-issue synergistic processor element of a CELL processor is developed with 20.9 million transistors in 14.8mm2 using a 90nm SOI technology. CMOS static gates implement the majority of the logic. Dynamic circuits are used in critical areas, occupying 19% of the nonSRAM area. ISA, microarchitecture and physical implementation are tightly coupled to achieve a compact and power efficient design. Correct operation has been observed up to 5.6GHz at 1.4V supply and 56°C.
Keywords :
CMOS logic circuits; VLSI; integrated circuit design; logic design; logic gates; microprocessor chips; parallel processing; silicon-on-insulator; 1.4 V; 32 bit; 5.6 GHz; 56 C; 90 nm; CELL processor; CMOS static gates; SOI technology; VLSI system; circuit design; multi core processor; nonSRAM area; power efficient design; synergistic processor element; CMOS logic circuits; CMOS technology; Circuit synthesis; Clocks; Delay; Design optimization; Frequency; Ground penetrating radar; Latches; Programmable logic arrays;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560049
