DocumentCode :
2799572
Title :
IMF: interconnect-driven multilevel floorplanning for large-scale building-module designs
Author :
Chen, Tung-Chieh ; Chang, Yao-Wen ; Lin, Shyh-Chang
Author_Institution :
Graduate Inst. of Electron. Eng., National Taiwan Univ., Taipei, Taiwan
fYear :
2005
fDate :
6-10 Nov. 2005
Firstpage :
159
Lastpage :
164
Abstract :
We present in this paper, a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilevel framework that adopts the "V-cycle" framework: bottom-up coarsening followed by top-down uncoarsening, in contrast, IMF works in the "Λ-cycle" manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on mm-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and thus the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. We also propose an accelerative fixed-outline floorplanning (AFF) to speed up wirelength minimization under the outline constraint. Experimental results show that IMF consistently obtains the best floorplanning results with the smallest wirelength for large-scale building-module designs, compared with all publicly available floorplanners. In particular, IMF scales very well as the circuit size increases. The Λ-cycle multilevel framework outperforms the V-cycle one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the Λ-cycle framework considers the global configuration first and then processes down to local ones level by level and thus the global effects can be handled at earlier stages. The Λ-cycle multilevel framework is general and thus can be readily applied to other problems.
Keywords :
circuit optimisation; integrated circuit interconnections; integrated circuit layout; Λ-cycle multilevel framework; bottom-up coarsening; crosstalk optimization; exact net-weight modeling; fixed-outline floorplanning; global circuit effects; global interconnections; interconnect-driven multilevel floorplanning; interconnection optimization; iterative partitioning; large-scale building-module designs; top-down partitioning stage; top-down uncoarsening; wirelength minimization; Chip scale packaging; Clustering algorithms; Design engineering; Integrated circuit interconnections; Large-scale systems; Law; Legal factors; Merging; Simulated annealing; Transistors;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
Type :
conf
DOI :
10.1109/ICCAD.2005.1560057
Filename :
1560057
Link To Document :
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