Can digital GaAs be used in a space environment? A look at single event upset in GaAs

Author

Weatherford, T.R. ; Campbell, A.B. ; McMorrow, D. ; Langworthy, J.B. ; Stapor, W.J. ; Knudson, A.R. ; Petersen, E.L. ; Wilson, D. ; Tran, L.

Author_Institution

US Naval Res. Lab., Washington, DC, USA

fYear

1991

fDate

20-23 Oct. 1991

Firstpage

79

Lastpage

82

Abstract

The vulnerability to SEU (single event upset) of devices produced by standard GaAs processes is too great to allow their use in space applications without some type of mitigation technique. GaAs foundries can provide solutions for the short term by providing SEU hardened designs incorporating redundancy for latches in standard cell families and gate arrays. As research progresses, techniques are expected to be found to reduce charge enhancement effects in GaAs FETs. Industry-developed solutions for sidegating and backgating effects may also improve SEU sensitivity. Designs intended for SEU environments can incorporate several mitigation techniques to provide satisfactory operation. However, hardening at the device may provide the best performance option.<>

Keywords

III-V semiconductors; aerospace instrumentation; circuit reliability; digital integrated circuits; gallium arsenide; monolithic integrated circuits; radiation hardening (electronics); redundancy; GaAs FETs; SEU hardened designs; backgating effects; charge enhancement effects; digital GaAs; gate arrays; mitigation techniques; redundancy; sidegating; single event upset; space environment; standard cell families; Atomic layer deposition; Capacitance; Gallium arsenide; Latches; MESFETs; Protons; Single event upset; Space technology; Substrates; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1991. Technical Digest 1991., 13th Annual

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-0196-X

Type

conf

DOI

10.1109/GAAS.1991.172638

Filename

172638