A SystemVerilog approach in system validation with affine arithmetic

Author

Mialtu, R.

Author_Institution

SC Infineon Technol. Romania & Co. SCS, Bucharest, Romania

Volume

2

fYear

2012

fDate

15-17 Oct. 2012

Firstpage

407

Lastpage

410

Abstract

This paper introduces an original approach to system modeling for performance analysis and optimization. The method presented herein theoretical background is the mathematical field of affine arithmetic chosen for its intrinsic data representation optimal to analysis of the mitigation of variations and refinement of deviations and error analysis. The chosen language of SystemVerilog is beneficial for it is allowing the integration of the validation process and of the verification process for the specific class of mixed signal electrical circuits and systems.

Keywords

digital arithmetic; electronic engineering computing; error analysis; hardware description languages; mixed analogue-digital integrated circuits; optimisation; SystemVerilog approach; affine arithmetic; error analysis; mixed signal electrical circuits; optimization; performance analysis; system validation; Analytical models; Approximation methods; Arrays; Mathematical model; Noise; Optimization; Standards; SystemVerilog; affine arithmetic; system modelling; validation;

fLanguage

English

Publisher

ieee

Conference_Titel

Semiconductor Conference (CAS), 2012 International

Conference_Location

Sinaia

ISSN

1545-857X

Print_ISBN

978-1-4673-0737-6

Type

conf

DOI

10.1109/SMICND.2012.6400746

Filename

6400746