Flip-flop insertion with shifted-phase clocks for FPGA power reduction

Although the LUT (look-up table) size of FPGAs has been optimized for general applications, complicated designs may contain a large number of cascaded LUTs between flip-flops. This results in unwanted glitch propagation along the LUTs, and wastes power. This paper proposes a flip-flop insertion, we propose insertion of new flip-flops between adjacent existing flip-flops to minimize glitch propagation and power loss. Each new flip-flop is timed by a phase-shifted clock with the phase calculated from the delays of LUTs and routing paths. This is different from traditional retiming methods that use the original clock or an 180-degree clock for the new flip-flops, and thus alters the original pipeline structure and synchronization. We start from a post-layout design, retiming its clock frequency and timing behavior. Multiple flip-flop insertion is an NP-complete problem because each new flip-flop affects the delays in the design. We have devised a glitch generation and propagation model for LUT-based FPGAs that take account of path delays while supporting reasonable complexity. We propose effective heuristics for flip-flop insertion and clock phase selection. Full-chip measurements, including all the overheads associated with the inserted flip-flops, show that our approach shows up to 38% of the total dynamic power. We have analyzed our scheme, showing the mechanics of clock assignment and glitch minimization, and the sources of power reduction.