Acyclic modeling of combinational loops

This paper presents a method to convert gate-level combinational loop into an acyclic circuit, if the combinational loop is not oscillatory. Combinational loops breach design methodologies, because they can involve undesirable circuit behavior and can possibly lead to oscillations based on the external stimuli to the loops. However, for designs compiled using automated synthesis-compiler, these loops are very likely to appear in the generated gate-level designs. We present a modeling of combinational loops as state holding elements and break non oscillatory loops using a level sensitive latch. Apart from modeling combinational loops consisting of gates, the algorithm also converts the loops through design latches. The increase in design area, due to the loop conversion, has an upper bound of twice the size of the original feedback path. However, in case of multiply nested feedback paths, each path is treated separately. Unlike previous work that converts cyclic combinational logic where the feedback is not exercised, this paper presents an algorithm to identify the stateful "latch" behavior in a class of feedback logic (non-oscillatory, monotonic). A conversion algorithm replaces such feedback logic by an equivalent circuit comprising explicit latches and acyclic combinational logic. The replacement circuit has an identical behavior as the original stateful feedback logic.