10 Gbit/s bit-synchronizer with automatic retiming clock alignment using quantum well AlGaAs/GaAs/AlGaAs technology

Author

Wennekers, P. ; Nowotny, U. ; Huelsmann, A. ; Kaufel, G. ; Koehler, K. ; Raynor, B. ; Schneider, J.

Author_Institution

Fraunhofer Inst. for Appl. Solid State Phys., Freiburg, Germany

fYear

1991

fDate

20-23 Oct. 1991

Firstpage

217

Lastpage

220

Abstract

A 10 Gb/s bit-synchronizer circuit has been fabricated using an enhancement/depletion 0.3 mu m recessed-gate AlGaAs/GaAs/AlGaAs quantum well FET process. The differential gain of the phase comparator circuit is measured to be 371 mV/rad. The phase margins for monotonous phase comparison are -54/+21 degree relative to the in bit cell center position of the clock edge. The chip has a power dissipation of 160 mW at a supply of 1.90 V.<>

Keywords

III-V semiconductors; aluminium compounds; clocks; digital integrated circuits; field effect integrated circuits; gallium arsenide; phase comparators; synchronisation; 0.3 micron; 10 Gbit/s; 160 mW; AlGaAs-GaAs-AlGaAs; automatic retiming clock alignment; bit-synchronizer circuit; differential gain; enhancement/depletion recessed gate technology; in bit cell center position; phase comparator circuit; phase margins; power dissipation; quantum well FET process; Circuits; Clocks; Etching; FETs; Fabrication; Gallium arsenide; Optical pulses; Phase measurement; Sampling methods; Semiconductor device measurement;

fLanguage

English

Publisher

ieee

Conference_Titel

Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 1991. Technical Digest 1991., 13th Annual

Conference_Location

Monterey, CA, USA

Print_ISBN

0-7803-0196-X

Type

conf

DOI

10.1109/GAAS.1991.172676

Filename

172676