DocumentCode :
2800656
Title :
Improving the efficiency of static timing analysis with false paths
Author :
Zhou, Shuo ; Yao, Bo ; Chen, Hongyu ; Zhu, Yi ; Cheng, Chung-Kuan ; Hutton, Mike ; Collins, Truman ; Srinivasan, Sridhar ; Chou, Nanchi ; Suaris, Peter
Author_Institution :
California Univ., La Jolla, CA, USA
fYear :
2005
fDate :
6-10 Nov. 2005
Firstpage :
527
Lastpage :
531
Abstract :
We improve the efficiency of static timing analysis when false paths are considered. The efficiency of timing analysis is critical for the performance driven optimization program because timing analysis is invoked heavily in the inner loop. However, when false paths are dealt in timing analysis, a large number of tags need to be created and propagated, and thus deteriorated the efficiency. In this paper, we minimize the number of the tags through a biclique covering approach, which iteratively removes a tag if the false path information in the tag is covered by the union of other tags. The produced tags remove the false path timing and guarantee to cover the true path timings. Since the minimum biclique covering of the general bipartite graph is NP complete, we use a minimal degree ordering approach to perform the biclique covering minimization. The experimental results show significant reduction on the number of tags.
Keywords :
circuit analysis computing; circuit optimisation; timing; NP complete; biclique covering; bipartite graph; false path; false sub-graphs; static timing analysis; tag minimization; Algorithm design and analysis; Bipartite graph; Circuit optimization; Cost function; Graphics; Merging; Minimization; Performance analysis; Timing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
Type :
conf
DOI :
10.1109/ICCAD.2005.1560123
Filename :
1560123
Link To Document :
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