Design of self-clocked sequential circuits using logic cell arrays

A systematic method of design for asynchronous sequential circuits using Logic Cell Arrays such as XILINX 2000 or 3000 series is presented. In this method each state is represented by a separate flip-flop whose clock signal is generated locally. State machines of considerable size can be accommodated on a single chip and in most applications the outputs are readily available on the chip without the need for external decoding of the states. Problems of races and hazards, commonly associated with asynchronous circuits, are eliminated. The method is applied to the design of a VME Bus Requester and the use of CAD packages to simulate such designs are discussed