"Flying-Adder" PLL Based Synchronization Mechanism for Data Packet Transport

A novel frequency synthesis architecture, Flying-Adder architecture, has been developed in recent years. Compared with conventional PLL based frequency synthesis techniques, this new method has many unique features. Among them, the two most distinguishing ones are its instantaneous response speed and very fine frequency resolution. These features can be especially beneficial to application of data smoothing in packet-oriented transport systems. In this paper, this Flying-Adder PLL based synchronization approach is demonstrated through two real examples.