Circuit modeling of carbon nanotube interconnects and their performance estimation in VLSI design

Author

Arijit Raychowdhury ; Roy, K.

Author_Institution

Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

fYear

2004

fDate

24-27 Oct. 2004

Firstpage

122

Lastpage

123

Abstract

The International Technology Roadmap for Semiconductors (ITRS) emphasizes on the need for reliable, high speed interconnects for the future technology generations. Innovative materials are being extensively studied and carbon nanotubes (CNTs) have emerged as a promising material for future generation ICs. Recent experiments have shown that CNTs can handle extremely high current densities (/spl sim/10/sup 10/ A/cm/sup 2/) for hours without significant degradation of performance. In this paper we have developed a comprehensive RLC transmission line model for metallic CNTs (Burke, 2002), and evaluated their performance in high speed VLSI design.

Keywords

RLC circuits; VLSI; carbon nanotubes; high-speed integrated circuits; integrated circuit interconnections; integrated circuit modelling; transmission lines; carbon nanotube interconnects; circuit modeling; comprehensive RLC transmission line model; high current density; high speed VLSI design; metallic CNTs; performance estimation; Integrated circuit interconnections; Integrated circuit modeling; Transmission lines; Very-large-scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on

Conference_Location

West Lafayette, IN, USA

Print_ISBN

0-7803-8649-3

Type

conf

DOI

10.1109/IWCE.2004.1407357

Filename

1407357