Title :
Statistical timing analysis with two-sided constraints
Author :
Heloue, Khaled R. ; Najm, Farid N.
Author_Institution :
Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada
Abstract :
Based on a timing yield model, a statistical static timing analysis technique is proposed. This technique preserves existing methodology by selecting a "device file setting" that takes into account within-die statistical variations, and with which to run traditional static timing analysis in order to meet the desired yield. Using process-specific "generic paths" representing critical paths in a given process technology, our approach can be used early in the design process, most importantly during the pre-placement phase. Within-die variations are taken care of using a simple model that assumes positive correlation, which leads to upper and lower bounds on the timing yield. Our approach also handles both setup and hold timing constraints.
Keywords :
integrated circuit design; semiconductor process modelling; statistical analysis; timing; design process; device file setting; pre-placement phase; process technology; process-specific generic paths; statistical timing analysis; timing yield model; two-sided constraints; within-die statistical variations; Circuit synthesis; Circuit testing; Delay; Design optimization; Feedback; Integrated circuit yield; Microprocessors; Principal component analysis; Process design; Timing;
Conference_Titel :
Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
Print_ISBN :
0-7803-9254-X
DOI :
10.1109/ICCAD.2005.1560178