• DocumentCode
    2801706
  • Title

    Architecture and details of a high quality, large-scale analytical placer

  • Author

    Kahng, Andrew B. ; Reda, Sherief ; Wang, Qinke

  • Author_Institution
    Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
  • fYear
    2005
  • fDate
    6-10 Nov. 2005
  • Firstpage
    891
  • Lastpage
    898
  • Abstract
    Modern design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities. With these complexities in mind, placers are faced with the burden of finding an arrangement of placeable objects under strict wirelength, timing, and power constraints. In this paper we describe the architecture and novel details of our high quality, large-scale analytical placer. The performance of our placer has been recently recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (i) a new clustering architecture, (ii) a dynamically adaptive analytical solver, and (iii) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets. On average, our results are better than the best published results by 3%, 14%, and 6% for the IBM ISPD ´04, ICCAD ´04, and ISPD ´05 benchmark sets respectively. One of the goals of this paper is to also provide enough details to enable possible future replication of our methods.
  • Keywords
    VLSI; integrated circuit design; ISPD-2005 placement contest; VLSI; adaptive analytical solver; clustering architecture; fixed blocks; integrated circuit layout; large-scale analytical placer; legalization scheme; movable blocks; placeable objects; power constraint; timing constraint; whitespace resources; wirelength constraint; Circuits; Computer architecture; Computer science; Engines; Large-scale systems; Runtime; Service oriented architecture; Timing; Very large scale integration;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Computer-Aided Design, 2005. ICCAD-2005. IEEE/ACM International Conference on
  • Print_ISBN
    0-7803-9254-X
  • Type

    conf

  • DOI
    10.1109/ICCAD.2005.1560188
  • Filename
    1560188