Hole mobilities and electrical characteristics of Ω- gated silicon nanowire array FETs with 〈110〉 - and 〈100〉 - channel orientation

We report on the fabrication and electrical characterization of Ω-gated nanowire (NW) array pFETs on SOI. Devices with gate lengths of L = 400nm and L = 2 μm and 〈110〉 - and 〈100〉 - channel orientations were fabricated using a top-down approach. Each device consists of up to 1500 NWs with a crosssection of 20 × 20 nm². The devices feature excellent electrical characteristics with high on-currents, I_on/I_off ratio of 10⁸, close to ideal inverse sub-threshold slopes of 64 mV/dec and low series resistances of 200 Ω. NW-array FETs aligned along the 〈110〉 - direction showed ×1.4 larger on-currents and ×1.3 higher transconductances compared to devices aligned along the 〈100〉 - direction. Hole mobilities in NW-array pFETs with 〈110〉 - and 〈100〉 - channel orientation were measured employing a split-CV technique. NW FETs aligned along a 〈110〉 - direction display a 40% higher hole mobility at low as well as at high vertical electric field compared to devices along the 〈100〉 - direction.