Register Versioning: A Low-Complexity Implementation of Register Renaming in Out-of-Order Microarchitectures

Register renaming and associated register management mechanisms represent a significant source of complexity in out-of-order micro architectures. We propose the use of register versioning to simplify this logic. Hardware-supported register versioning permits monotonically increasing version numbers to uniquely identify each uncommitted instance of an architectural register. Register versioning replaces the physical register file with a simpler structure that integrates the physical register file with an architectural register file, both having the same number of entries, namely the number of architectural registers. The integrated structure uses local bitcell level connections to commit results to a precise state, saving a significant amount of energy in the process. We also propose optimizations to the proposed mechanism. Despite drastic data path simplification, our proposed architecture performs within 6% of traditional out-of-order processors and within 4% of the performance of a SMT processor with 4 threads.