A simulation-based study of sensitivity to parameter fluctuations of silicon Tunnel FETs

In this paper we study the sensitivity to parameter fluctuations for an optimized double-gate silicon Tunnel FET with a high-k gate dielectric. The impacts of the variability of the dielectric thickness, doping profile at the tunnel junction, silicon body thickness, alignment of the gate dielectric to the tunnel junction, device length, and band gap at the tunnel junction, on the device performance are systematically studied. One parameter is varied at a time to show the resulting fluctuations of the device characteristics. Gate dielectric thickness and doping junction width are pinpointed as the parameters requiring the tightest control during Tunnel FET fabrication in order to limit characteristic fluctuations. Body thickness and gate dielectric alignment with the tunnel junction may also need tight control depending on whether the target values are within a range where the characteristics are highly sensitive.