Can digital tests be used on analogue integrated circuits?

The increasing availability and reduced cost of mixed analogue/digital ASICs means that it is possible to design and fabricate such circuits in small quantities in a short space of time. However the generation of tests to determine whether the chips have been correctly manufactured is not so straightforward. Purely digital circuits are usually tested using the stuck-at fault model to generate test patterns which highlight faulty devices, but no such process exists for mixed-signal circuits where the interface between digital for and analogue sections may be inaccessible to test probes. Design-for-test techniques may be used to overcome this problem by including test circuitry on the chip that allows the digital and analogue sections to be tested independently; but this involves the use of additional pins, silicon and design time, all of which are unacceptable in a low-volume, short-timescale project. Work at Lancaster is looking at ways of avoiding these complications by using pseudo-digital tests to check the functionality of a complete chip (which may be composed entirely of analogue cells) using readily available digital test equipment. This paper discusses the approach used and the fault cover that can be expected