Analysis of thermal vias in high density interconnect technology

An analytical approach is presented for the thermal modeling of via networks used in removing heat from chips in high density multichip module designs. The thermal resistances of the components making up a typical via network cell are accurately determined by closed form expressions. The complete thermal resistance between the die and substrate can be determined by constructing the unit cells in a combination of series and parallel paths, allowing for the thermal spreading effect through the via network, and the epoxy and planarizing layer thermal resistances. Computed predictions are compared with numerical and experimental results, and good agreement was achieved by using this accurate and simple methodology