Title :
Low-drift InP MISFETs
Author :
Post, G. ; Falcou, A. ; Dimitriou, P. ; Courant, J.L. ; Scavennec, A.
Author_Institution :
Lab. de Bagneux, CNET, France
Abstract :
InP MISFETs have been fabricated, based on ion-implantation in SI substrates and photo CVD SiO2 deposition for the dielectric gate. Reduced drift of the characteristics has been obtained by careful surface preparation before SiO2 deposition at low temperature (180°C) and post deposition annealing. E-D inverters as well as ring oscillators have been fabricated with gate propagation delay time (300 ps) limited mainly by the capacitance of the non self aligned gate. Depletion-mode MISFETs find applications in transmitter and receiver optoelectronic circuits
Keywords :
III-V semiconductors; chemical vapour deposition; indium compounds; insulated gate field effect transistors; ion implantation; logic gates; oscillators; 180 degC; 300 ps; E-D inverters; InP; InP-SiO2; MOSFETs; SI substrates; capacitance; depletion mode MISFETs; dielectric gate; drift reduction; gate propagation delay time; ion-implantation; low drift MISFETs; photo CVD SiO2 deposition; post deposition annealing; receiver optoelectronic circuits; ring oscillators; semiconductors; surface preparation; transmitter optoelectronic circuits;
Conference_Titel :
InP Based Materials, Devices and Integrated Circuits, IEE Colloquium on
Conference_Location :
London
