Title :
Code for the 3D simulation of nanoscale semiconductor devices, including drift-diffusion and ballistic transport in 1D and 2D subbands, and 3D tunneling
Author :
Fiori, G. ; Iannaccone, G.
Author_Institution :
Dipt. di Ingegneria dell´´Informazione: Elettronica, Informatica, Telecomunicazioni, Universita degli studi di Pisa, Italy
Abstract :
Device modeling tools capable to address different degrees of quantum confinement and different transport regimes are required to address both MOSFETs at the end of the ITRS Roadmap and alternative device structures. In this work, we present a code based on the self-consistent solution of the i) many particle Schrodinger equation based on density functional theory, it) on the nonlinear Poisson equation, and ii) on the continuity equation for electrons and holes, in the cases of both drift-diffusion and ballistic transport regimes. In addition, different regions with arbitrary degrees of quantum confinement may be considered, and transport in such regions is consequently computed. We present an example for each of the simulation of: 1) a single electron transistor defined by split gates on an AlGaAs/GaAs heterostructure, and 2) a silicon nanowire transistor.
Keywords :
III-V semiconductors; MOSFET; Poisson equation; Schrodinger equation; ballistic transport; circuit simulation; density functional theory; electronic engineering computing; gallium arsenide; nanoelectronics; nanowires; semiconductor device models; semiconductor heterojunctions; tunnelling; 1D subband; 2D subband; 3D simulation; 3D tunneling; AlGaAs; AlGaAs heterostructure; GaAs; GaAs heterostructure; MOSFET; ballistic transport; continuity equation; density functional theory; device modeling; drift-diffusion; electrons; holes; many particle Schrodinger equation; nanoscale semiconductor devices; nonlinear Poisson equation; quantum confinement; self-consistent solution; silicon nanowire transistor; single electron transistor; split gates; Gallium compounds; MOSFETs; Partial differential equations; Quantum theory; Semiconductor device modeling; Semiconductor heterojunctions; Tunneling;
Conference_Titel :
Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on
Conference_Location :
West Lafayette, IN, USA
Print_ISBN :
0-7803-8649-3
DOI :
10.1109/IWCE.2004.1407407