DocumentCode
2802718
Title
Numerical simulation for direct tunneling current in poly-Si-gate MOS capacitors
Author
Okamoto, M. ; Mori, N.
Author_Institution
Dept. of Electron. Eng., Osaka Univ., Suita, Japan
fYear
2004
fDate
24-27 Oct. 2004
Firstpage
235
Lastpage
236
Abstract
To provide adequate control of short channel effects, gate-oxide thickness of MOSFETs is reduced nearly in proportional to channel length. For sub-100 nm channel lengths, an oxide thickness, t/sub ox/, of less than a few nm is needed. In such a device, gate current is significant even for low gate bias region due to direct tunneling of electrons through the oxide. To simulate direct tunneling current, quantum effects, such as (1) tunneling transition rate and (2) standoff distance due to the quantum confinement of electrons in the channel region, should be properly taken into account. For poly-Si-gate devices, (3) a depletion-layer in the gate region should also be taken into account. Recently, Price (2004) demonstrated that the Gamow formulation can be applied to analysis of the escape of electrons from the channel region into the gate. In the present study, we have numerically simulated direct tunneling current in poly-Si-gate MOS capacitors by integrating the Gamow method into a Schrodinger-Poisson solver. We especially focus on the boundary condition for the confined states that gives natural results.
Keywords
MOS capacitors; MOSFET; Poisson equation; Schrodinger equation; field effect devices; nanoelectronics; numerical analysis; semiconductor device models; tunnelling; Gamow formulation; Gamow method; MOSFET; Schrodinger-Poisson solver; channel length; channel region; confined states; direct tunneling current; electron escape; electron tunneling; gate current; gate region depletion-layer; gate-oxide thickness; numerical simulation; polySi-gate MOS capacitors; polySi-gate devices; quantum confinement; quantum effects; standoff distance; tunneling transition rate; MOS capacitors; MOSFETs; Numerical analysis; Partial differential equations; Quantum theory; Semiconductor device modeling; Tunneling;
fLanguage
English
Publisher
ieee
Conference_Titel
Computational Electronics, 2004. IWCE-10 2004. Abstracts. 10th International Workshop on
Conference_Location
West Lafayette, IN, USA
Print_ISBN
0-7803-8649-3
Type
conf
DOI
10.1109/IWCE.2004.1407413
Filename
1407413
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