Title :
Real-time 4x4 intraframe prediction architecture for a H.264 decoder
Author :
Staehler, Wagston Tassoni ; Susin, Altamiro Amadeu
Author_Institution :
UFRGS, Alegre
Abstract :
Multimedia systems need each time more video quality in order to respond new demands of video conferencing, digital TV, video storage, etc. At the same time and conflictingly, the need of better network/bandwidth utilization increases. To answer both demands,H.264-AVC was developed. This new video coding standard, accepted internationally, has a huge compression rate what make possible the transmission of very high quality videos over the actual frequency bandwidth or four parallel channels with standard resolution. One of its improvements over previous standards that make this excellent compression rate possible is the intraframe prediction module. This paper presents a hardware implementation of a 4times4 intraframe prediction decoder. Despite the computational complexity of the standard and the constraints needed to compress high quality video, the presented architecture is able to decode HDTV (1920 times 1080 pixels) in real-time.
Keywords :
computational complexity; data compression; decoding; digital video broadcasting; image resolution; multimedia communication; teleconferencing; video coding; H.264 decoder; compression rate; computational complexity; digital TV; frequency bandwidth; multimedia systems; network-bandwidth utilization; parallel channels; real-time 4x4 intraframe prediction architecture; standard resolution; video coding standard; video conferencing; video quality; video storage; Bandwidth; Computational complexity; Decoding; Digital TV; Frequency; Hardware; Multimedia systems; Video coding; Video compression; Videoconference; Digital TV; FPGA-based Design; H.264; Image Processing;
Conference_Titel :
Telecommunications Symposium, 2006 International
Conference_Location :
Fortaleza, Ceara
Print_ISBN :
978-85-89748-04-9
Electronic_ISBN :
978-85-89748-04-9
DOI :
10.1109/ITS.2006.4433309