Automatic SoC Level Test Path Synthesis Based on Partial Functional Models

While system level test was a topic of extremely high interest during the last decades, the cost of the test program development was continuously growing. The restricted capabilities of Boundary Scan (BS) with respect of such modern challenges as dynamic (timing-accurate), at-speed and high speed testing as well as in-system diagnosis of functional failures create considerable troubles for test engineers in production environments. In this paper, we propose a general modeling methodology for automatic test path synthesis for microprocessor SoC-based systems, that drastically reduces the cost of the test program. The new automation methodology forms a complementary solution to traditional boundary scan by overcoming its weaknesses at no investment into system design process.