Hardware Acceleration for 3D Image Reconstruction

This work presents a hardware acceleration scheme for a 3D reconstruction method, targeting demanding dynamic Integral Imaging applications. The architecture exploits parallel processing and minimizes memory operations by implementing an efficient metric and an extended-access memory scheme. The employed data reutilization technique reduces overall throughput allowing the use of a single FPGA. Results reveal that the hardware system accelerates the software method by an order of magnitude and its processing rate surpasses the typical rate of a dynamic Integral Imaging acquisition system, making it suitable for robust 3D image and video reconstruction applications.