DocumentCode :
2803476
Title :
Optimized Test Error Detection by Probabilistic Retest Recommendation Models
Author :
Kirmse, Matthias ; Petersohn, Uwe ; Paffrath, Elief
Author_Institution :
Dept. of Comput. Sci., Dresden Univ. of Technol., Dresden, Germany
fYear :
2011
fDate :
20-23 Nov. 2011
Firstpage :
317
Lastpage :
322
Abstract :
As a result of increasing test costs it becomes more and more attractive to improve the test process using modern machine learning techniques. Consequently, in our paper we focus on an essential part of the test process: efficient test error detection. Our proposed online test error detection approach is based on a novel die probability model, which is able to classify die runs as correct or erroneous solely based on their bins and the bins of adjacent dice on the wafer. To achieve this, an underlying bayesian network represents both, production caused bin relations of adjacent dice and test error influences on die binning. Based on the basic die probability model, we present three wafer retest recommendation models. Since they allow prompt analyses of wafer runs and deliver die or bin specific retest recommendations, they should enable a faster and more efficient test error detection than provided by standard detection methods like static bin limits or regular retests. To evaluate our approach, we used test data from a real semiconductor test process. In the our experiments we studied the basic detection performance of the die probability model and compared our wafer retest recommendation models to the standard strategies in terms of detection ratio, retest ratio and retest efficiency.
Keywords :
automatic test pattern generation; belief networks; error detection; integrated circuit testing; learning (artificial intelligence); probability; Bayesian network; adjacent dice; detection ratio; die binning; die probability model; machine learning; online test error detection; optimized test error detection; probabilistic retest recommendation models; retest efficiency; retest ratio; semiconductor test process; static bin limits; wafer retest recommendation models; Accuracy; Bayesian methods; Measurement uncertainty; Production; Random variables; Semiconductor device modeling; Bayesian Networks; Test error detection;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Test Symposium (ATS), 2011 20th Asian
Conference_Location :
New Delhi
ISSN :
1081-7735
Print_ISBN :
978-1-4577-1984-4
Type :
conf
DOI :
10.1109/ATS.2011.11
Filename :
6114749
Link To Document :
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