A New Test Paradigm for Semiconductor Memories in the Nano-Era

Due to rapid and continuous technology scaling, faults in semiconductor memories (and ICs in general) are becoming pervasive and weak rather than strong, a weak fault is a fault that escape the test program (because it does not cause an error/system failure). However, multiple weak faults may cause an error during the application. Components with weak faults which fail at board and system level are sent to suppliers, but only to have them returned back as No Trouble Found (NTF). This is because the conventional memory test approach assumes the presence of a single defect at a time causing a strong fault (hence an error), and is therefore unable to deal with weak faults. This paper presents a new memory test approach able to detect weak faults, it is based on assuming the presence of multiple weak faults at a time in a memory system rather than a single strong fault at a time. Being able to detect weak faults reduces the number of escapes, hence also the number of NTFs. The experimental analysis done using SPICE simulation for a case of study show that when assuming two simultaneous weak faults, the missing (defect) coverage can be reduced with 10% as compared with the conventional approach.