Testing for Parasitic Memory Effect in SRAMs

Parasitic memory effect can occur due to the impact of parasitic node capacitances and faulty node voltages on the electrical behavior of SRAMs. This memory effect can cause detectable faults to become undetectable using existing industrial tests. This paper analyzes, evaluates and identifies the unique detection conditions for faults in SRAMs. It demonstrates the limitation of existing industrial tests that do not take the impact of parasitic memory effect into consideration. Finally, the paper presents March SME, a memory test that detects SRAM static faults in the presence of parasitic memory effect.