DocumentCode
2804428
Title
Study of GaN HEMTs electrical degradation by means of numerical simulations
Author
Di Lecce, Valerio ; Esposto, Michele ; Bonaiuti, Matteo ; Fantini, Fausto ; Chini, Alessandro
Author_Institution
Dept. of Inf. Eng., Univ. of Modena & Reggio Emilia, Modena, Italy
fYear
2010
fDate
14-16 Sept. 2010
Firstpage
285
Lastpage
288
Abstract
In this paper, we investigate the effects of dc stress on GaN high-electron mobility transistors (HEMTs) by means of numerical simulations. Following stress tests showing a degradation of static characteristics (dc), the formation of an electron trap in the AlGaN barrier layer was related to the observed degradation according to the results obtained from numerical simulations carried out by introducing a trapping region underneath the gate edge. The worsening of the device dc performance is evaluated by changing the extension of the degraded region and the trap concentration while studying the variation of parameters like the saturated drain current IDSS, the output conductance gO, and the device transconductance gM. An increase in the trap concentration induces a worsening of any of the above mentioned parameters; an increase in the extension of the degraded region induces a degradation of IDSS and gM, but can reduce gO.
Keywords
III-V semiconductors; gallium compounds; high electron mobility transistors; numerical analysis; semiconductor device reliability; semiconductor device testing; AlGaN; GaN; HEMT; barrier layer; dc stress; electrical degradation; electron trap; high-electron mobility transistors; numerical simulations; stress tests; Aluminum gallium nitride; Charge carrier processes; Degradation; Gallium nitride; HEMTs; Logic gates; MODFETs;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European
Conference_Location
Sevilla
ISSN
1930-8876
Print_ISBN
978-1-4244-6658-0
Type
conf
DOI
10.1109/ESSDERC.2010.5618358
Filename
5618358
Link To Document