UT2B-FDSOI device architecture dedicated to low power design techniques

In this paper, a new ultra-thin body and BOX (UT2B) fully-depleted (FD) silicon-on-insulator (SOI) device architecture based on a stacked back plane (BP) and WELL below the BOX is presented. The proposed device has been developed to boost the gate-to-channel electrostatic control and to be compatible with the adaptive body biasing (ABB) techniques for low power applications. The concept viability and the device electrical characteristics have been demonstrated by TCAD simulations at L_G=30nm. The electrical characteristics have been assessed with regular UTB-FDSOI devices for various BOX thicknesses (T_BOX). It is shown that the body factor (γ) is for both nMOS and pMOS devices higher than 170mV/V at 10nm of T_BOX. On a ring oscillator (RO), the proposed device architecture leads to lower static power dissipation (between a factor 1.2 and 6.7) for a similar propagation delay, compared to devices without BP/WELL.