Title :
DDR SDRAM Memory Controller for Digital TV Decoders
Author :
Siqueira, Hadley M. ; Silva, I.S. ; Kreutz, Marcio E. ; Correa, Edgard F.
Author_Institution :
Dept. of Inf. & Appl. Math., Fed. Univ. of Rio Grande do Norte - UFRN, Natal, Brazil
Abstract :
This paper presents a multichannel DDR SDRAM memory controller to be used as an IP in a set-top box compliant with Brazilian Digital Television System. A set-top box is comprised by modules that access an external memory sharing the same bus. Thus, it is necessary a multichannel memory controller to schedule accesses. This work shows that the implemented system running at 100 MHz can achieve the necessary bandwidth to decode and exhibit HD 1080p resolution videos at 30 frames per second.
Keywords :
DRAM chips; digital television; set-top boxes; television; Brazilian digital television system; IP; digital TV decoders; frequency 100 MHz; multichannel DDR SDRAM memory controller; set-top box; Bandwidth; Central Processing Unit; Decoding; Graphics; Real time systems; SDRAM; Videos; DDR SDRAM; digital TV; memory controller; set-top box;
Conference_Titel :
Computing System Engineering (SBESC), 2011 Brazilian Symposium on
Conference_Location :
Florianopolis
Print_ISBN :
978-1-4673-0427-6
DOI :
10.1109/SBESC.2011.16
