Optimization of tunnel FETs: Impact of gate oxide thickness, implantation and annealing conditions

Author

Leonelli, D. ; Vandooren, A. ; Rooyackers, R. ; De Gendt, S. ; Heyns, M.M. ; Groeseneken, G.

Author_Institution

Imec, Leuven, Belgium

fYear

2010

fDate

14-16 Sept. 2010

Firstpage

170

Lastpage

173

Abstract

We show the impact of process parameters on the electrical performance of complementary Multiple-Gate Tunneling Field Effect Transistors (MuGTFETs), implemented in a MuGFET technology compatible with standard CMOS processing. Firstly, the impact of the gate oxide thickness and implant doping conditions on the tunneling performance is analyzed and compared with TCAD simulations. Secondly, three different annealing conditions are compared: spike anneal, sub-ms laser anneal and low temperature anneal for Solid Phase Epitaxy Regrowth (SPER). Surprisingly, the SPER anneal shows a strong enhanced tunneling current with a record drive current of 46μA/μm at V_DD of -1.2V and I_OFF of 5pA/μm for Si pTFETs.

Keywords

CMOS integrated circuits; annealing; field effect transistors; semiconductor doping; technology CAD (electronics); tunnel transistors; tunnelling; MuGTFET technology; SPER anneal; TCAD simulation; annealing condition; drive current; electrical performance; gate oxide thickness; implant doping; low temperature anneal; multiple-gate tunneling field effect transistor; optimization; process parameter; solid phase epitaxy regrowth; spike anneal; standard CMOS processing; sub-ms laser anneal; tunnel FET; tunneling current; tunneling performance; Annealing; Doping; Logic gates; Performance evaluation; Semiconductor process modeling; Silicon; Tunneling;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Device Research Conference (ESSDERC), 2010 Proceedings of the European

Conference_Location

Sevilla

ISSN

1930-8876

Print_ISBN

978-1-4244-6658-0

Type

conf

DOI

10.1109/ESSDERC.2010.5618408

Filename

5618408