Title :
CALLAS/OASIS: Combining Behavioral and Register-Transfer Synthesis Systems
Author :
Pilsl, Michael ; Brglez, Franc
Author_Institution :
Siemens AG, Central Research Labs, Munich, Germany
Keywords :
Benchmark testing; Chip scale packaging; Control system synthesis; Design optimization; Electrical equipment industry; Hardware; Libraries; Logic design; Performance evaluation; Timing;
Conference_Titel :
System Theory, 1992. Proceedings. SSST/CSA 92. The 24th Southeastern Symposium on and The 3rd Annual Symposium on Communications, Signal Processing Expert Systems, and ASIC VLSI Design
Print_ISBN :
0-8186-2665-8
DOI :
10.1109/SSST.1992.712211
