Drain current variability in 45nm heavily pocket-implanted bulk MOSFET

Pocket architecture is a useful technique to eliminate short channel effects to provide smaller transistors sizes. However, it has been shown that it has an important drawback on mismatch. In this paper, the drain-current mismatch σ(ΔId/Id) is characterized for transistors without pockets and for heavily pocket-implanted transistors. These characterizations are performed from linear to saturation regime. A drain-current mismatch model as a function of drain voltage valid from weak to strong inversion region is also presented. For the first time, the drain current mismatch parameter is analyzed from linear to saturation regime for pocket devices. Thus, a comparison between transistors without pocket and transistors with pocket is performed and an important drain-current mismatch enhancement in the latter case is reported and discussed.