DocumentCode
2807059
Title
VT Matrix Multiply Design for MEMOCODE ´07
Author
Simpson, Eric ; Yu, Pengyuan ; Schaumont, Patrick ; Ahuja, Sumit ; Shukla, Sandeep
Author_Institution
Dept. of Electr. & Comput. Eng., Virginia Tech, Blacksburg, VA
fYear
2007
fDate
May 30 2007-June 2 2007
Firstpage
95
Lastpage
96
Abstract
This design presents a system optimized for complex matrix multiplications on the XUP Virtex-II board. Utilizing the GEZEL HW/SW co-simulation environment, the resulting system achieves ~25x speedup over a standard software only implementation. Further system level optimization (with DMA) results in the same coprocessor being speedup by at least another order of magnitude.
Keywords
field programmable gate arrays; matrix algebra; GEZEL HW-SW co-simulation environment; MEMOCODE ´07; VT matrix multiply design; XUP Virtex-II board; complex matrix multiplications; system level optimization; Algorithm design and analysis; Computer architecture; Concurrent computing; Control system synthesis; Coprocessors; Delay; Design optimization; Field programmable gate arrays; Read-write memory; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Formal Methods and Models for Codesign, 2007. MEMOCODE 2007. 5th IEEE/ACM International Conference on
Conference_Location
Nice
Print_ISBN
1-4244-1050-9
Type
conf
DOI
10.1109/MEMCOD.2007.371240
Filename
4231781
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