Title :
On PSL Properties Re-use in SoC Design Flow Based on Transaction Level Modeling
Author :
Bombieri, Nicola ; Fedeli, Andrea ; Fummi, Franco
Author_Institution :
STMicroelectronics, Agrate-Milano
Abstract :
In this paper the authors present some key concepts concerning the properties specification language (PSL) utilization in a system level verification flow for system on chip (SoC) designs. As transaction level modeling (TLM) is the de-facto reference model for SoC design flow, the authors evaluate PSL adoption in TLM context. How to save time and effort in the verification phase during system development steps and how to overcome global system verification limitations through a compositional approach are discussed. Two PSL-based techniques, "properties re-use" and "properties refinement", are described and compared in terms of refinement effort and simulation speed delay
Keywords :
formal verification; integrated circuit design; integrated circuit modelling; specification languages; system-on-chip; PSL properties reuse; SoC design; TLM; properties specification language; system development; system level verification flow; system on chip; transaction level modeling; Context modeling; Delay; Hardware; Performance analysis; Power system modeling; Protocols; Specification languages; System analysis and design; System testing; Timing;
Conference_Titel :
Microprocessor Test and Verification, 2005. MTV '05. Sixth International Workshop on
Conference_Location :
Austin, TX
Print_ISBN :
0-7695-2627-6
DOI :
10.1109/MTV.2005.15